Overview
XBurst is an innovative CPU technology developed by Ingenic Semiconductor to address the high performance and low power requirement of mobile internet devices.XBurst consists of 2 parts:
- Architecture level, XBurst implements MIPS instruction set and Ingenic’s own extension of SIMD instruction set.
- Implementation level, XBurst adopts a very power efficient pipeline micro-architecture. The processor consumes very small power while not sacrificing performance.
XBurst sets the new performance/area/power standard for embedded processors. For example, the first generation of XBurst, XBurst1 core implemented in 65nm LP technology, delivers 2.5 Dhrystone MIPS and 1.0-1.1GHz at 1.2V voltage, consumes less than 90mW power at full speed, and costs only 1.7mm2 silicon area (including 16K instruction cache, 16K data cache and power off switch circuit).
Roadmap
The roadmap of XBurst is shown in above picture. The first generation of the CPU, XBurst1 is completed. New generation with more powerful micro-architecture is under progress.
XBurst1 Specification
| |
0.13um |
|
65nm |
|
40nm |
| Architecture |
MIPS32 R2, SIMD extension |
| Micro-Architecture |
Single issue, 8 stage pipeline |
| DMIPS |
2.5 |
| Frequency |
528 -- 600MHz |
1.0GHz@1.2V |
1.3G-- 1.5G |
| Power |
0.22mW/MHz |
0.09mW/MHz |
0.05 mW/MHz |
| Area |
5.2mm2 |
1.7mm2 |
1.04mm2 |
* 0.13um and 65nm area includes 16K instruction cache and 16K data cache
* 40nm area includes 32K data cache and 32K instruction cache
XBurst1 History
| 2007 |
MIPS32 R1, |
used in JZ4730 SOC |
| 2008 |
+ SIMD |
used in JZ4740 SOC |
| 2009 |
+ SIMD2 |
used in JZ4750 SOC |
| 2010 |
+ FPU |
used in JZ4760 SOC |
| 2011 |
+ MIPS32 R2 |
used in JZ4770 SOC |
| 2012 |
+ SMP |
Will be used in 40nm SOC |